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[VHDL-FPGA-Verilog] Design_of_Traffic_Light_Control_System_Base_on_FPG

Description: 用VHDL 语言设计交通灯控制系统, 并在MAX+PLUS II 系统对FPGA/ CPLD 芯片进行下载, 由于生成的是集成化的数字电 路, 没有传统设计中的接线问题, 所以故障率低、可靠性高, 而且体积小。体现了EDA 技术在数字电路设计中的优越性。-The design method of traffic light control system by using Very- High- Speed Integrated Circuit Hardware Description Language (VHDL) is introduced, and the downloading of the controller design to the FPGA/ CPLD chip in MAX+PLUS II is fulfilled. As FPGA/ CPLD chips are based on large scale IC and there are no connection problems in the presented circuit, so the chips are re1iable and faults are less prone to happen, which shows the advantages of the EDA technology in digital circuits design.
Platform: | Size: 72704 | Author: li | Hits:

[VHDL-FPGA-Verilog] binary_to_decima

Description: 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL description，MAX+ plus Ⅱ can be used to run test
Platform: | Size: 1024 | Author: naf | Hits:

[VHDL-FPGA-Verilog] EXA01

Description: 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能 -VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
Platform: | Size: 41984 | Author: haongodng | Hits:

[VHDL-FPGA-Verilog] EXA02

Description: 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能-VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
Platform: | Size: 57344 | Author: haongodng | Hits:

[VHDL-FPGA-Verilog] EXA03

Description: 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能-VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
Platform: | Size: 38912 | Author: haongodng | Hits:

[VHDL-FPGA-Verilog] EXA04

Description: 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能-VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
Platform: | Size: 174080 | Author: haongodng | Hits:

[VHDL-FPGA-Verilog] EXA05

Description: 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能-VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
Platform: | Size: 94208 | Author: haongodng | Hits:

[Books] FPGAtaxier

Description: 摘要: 本文介绍了基于FPGA 的出租车计价器系统的功能、设计思想和实现, 该设计采用模块化自上而下的层次化设计,顶 层设计有5 个模块,各模块中子模块采用VHDL 或图形法设计。在Max+plusⅡ下实现编译、仿真等,最后成功下载到FPGA 芯 片中。完成了可预置自动计费、自动计程、计时、空车显示等多功能计价器。由于FPGA 具有高密度、可编程及有强大的软件 支持等特点,所以该设计具有功能强、灵活和可靠性高等特点,具有一定的实用价值。-Abstract: This paper introduces the function, design idea and realization of taximeter based on FPGA. The design takes the method of top-down and step by step. The whole system was divided into five modules that were described by VHDL or schematic diagram. By using Max+plus Ⅱ accomplish the compiler, simulator and so on. And then it can be downloaded to the FPGA chip . Achieve the goal to make a taximeter with the function of automatism count the money, the kilometer, the time and show empty car on a screen, ether. On FPGA high density and Programmable ability, you can see it has function better, modify convenient and high dependability. It has certainly practical value.
Platform: | Size: 206848 | Author: lu | Hits:

[VHDL-FPGA-Verilog] plj

Description: 数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（闸门时间）内，记录输入的脉冲的个数。我们可以通过改变记录脉冲的闸门时间来切换测频量程。本文利用EDA技术中的Max+plusⅡ作为开发工具,设计了基于FPGA的8位十进制频率计,并下载到在系统可编程实验板的EPF10K20TC144-4器件中测试实现了其功能。-Digital frequency meter is a kind of cyclical changes in the signal used to test the device operating frequency. The principle is that the specified unit of time (gate time), the record of the number of input pulses. We can change the record time to the gate pulse frequency measurement range switch. In this paper, the use of EDA technology Max+ plus Ⅱ as a development tool designed for FPGA-based 8-bit decimal frequency meter, and to download the experimental in-system programmable EPF10K20TC144-4 board test device to achieve its function.
Platform: | Size: 591872 | Author: 庄青青 | Hits:

[Communication] bym

Description: 在Max+plusΠ环境下用VHDL语言编写实现基于CPLD的CMI编译码器设计-In Max+ plusΠ environment using VHDL language CPLD-based design of CMI codecs
Platform: | Size: 1024 | Author: 莫迎宾 | Hits:

[VHDL-FPGA-Verilog] SY10

Description: 本文介绍了乐曲演奏电路的设计与实现中涉及的CPLD／FPGA可编程逻辑控件,开发环境MAX+PLUSⅡ,硬件描述语言HDL以及介绍了在MAX+PLUSⅡ的EDA 软件平台上, 一种基于FPGA 的乐曲发生器的设计方法, 并给出了设计的顶层电路图和底层模块的VHDL（或AHDL）源程序。该设计的正确性已通过硬件实验得到验证。 -The musical performance circuit’s design and implement Abstract: This paper introduced CPLD／FPGA programmable logic device, development entironment MAX+PLUSⅡ,hardware description language HDL which are related to the musical performance.And this paper introduced a design based on music generator by FPGA when MAX+PLUSⅡ, a EDA software is used. And a source program of VHDL (or AHDL)of the top schematics and the bottom module is supplied. The correctness of the design had been approved through hardware experiment.
Platform: | Size: 307200 | Author: guo | Hits:

[VHDL-FPGA-Verilog] thesecondsignalfunction

Description: 秒信号发生器，供初学者了解vhdl的编程方法，程序非常简单。编程环境使用Max+Plus IIV10.12-the second signal function
Platform: | Size: 4096 | Author: 孙天奇 | Hits:

[Other] MAXplusII

Description: CPLD数字电路设计--使用MAX+plusⅡ入门篇,学习MAX+plusII必备书籍。-CPLD digital circuit design- the use of MAX+ plus Ⅱ entry papers, study books MAX+ plusII necessary.
Platform: | Size: 20413440 | Author: 王海 | Hits:

[VHDL-FPGA-Verilog] ttt

Description: 该系统利用VHDL语言、PLD设计出租车计费系统，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了程序仿真。使其实现计费以及预置和模拟汽车启动、停止、暂停等功能，并动态扫描显示车费数目。-The system is the use of VHDL language, PLD design taxi billing system to MAX+ PLUS Ⅱ software as a development platform designed billing system procedures taxi and carried out a simulation program. To the achievement of pre-billing and simulation, as well as car to start, stop, pause and other functions, and dynamic scan shows the number of fares.
Platform: | Size: 183296 | Author: cch | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[Windows Develop] 8counter_origin

Description: This a design of 8bit binary counter using MAX PLUS PLUS.-This is a design of 8bit binary counter using MAX PLUS PLUS.
Platform: | Size: 2048 | Author: MK PARK | Hits:

[Books] EDA

Description: 介绍使用MAX+plus 2以及部分实验原理介绍，以及EDA开发工具。-On the use of MAX+ plus 2, as well as to introduce the principle part of the experiment, and the EDA development tools.
Platform: | Size: 657408 | Author: 徐婷婷 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Verilog HDL language taxi meter is designed so that it will have the time display, billing and simulated taxi start, stop, reset and other functions, and set up the dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the advantages of digital logic circuits. Source by the MAX+ PLUS Ⅱ software debugging, optimization, download EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system.
Platform: | Size: 211968 | Author: mindy | Hits:

[OpenGL program] MAX_Plus_II

Description: MAX_Plus_II应用超级教程 里边内容很多的 和它有关的一些器件，还有应用在其上的一些东东 总之不错-Super Guide MAX_Plus_II inside the contents of the application and it is a lot of some of the devices, as well as apply it to some good short Dongdong
Platform: | Size: 3318784 | Author: 李白 | Hits:

[Other] EDA

Description: 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器 内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
Platform: | Size: 11264 | Author: yuqingwei | Hits:
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